- Fab
- Semiconductor wafer fabrication plant
- Wafer
- Silicon wafer carrying numerous integrated circuit dies
- Lot
- Production management unit representing a lot of wafers
- Die
- Individual integrated circuit die on a wafer
Distinguish First: A Lot, a Wafer, and a Die
A lot is a production tracking batch, a wafer is the physical semiconductor disc, and a die is an individual chip unit. Lots can be split, merged, or reworked; wafers within the same lot may pass through different chambers.Wafer ID is the unique key for single-wafer tracking; slot numbers must be paired with carrier history and exact timestamps.
300 mm wafers are commonly transported in Front-Opening Unified Pods (FOUPs). Standard carriers have 25 slots, though other capacities exist; carrier capacity does not imply every lot is full. Purge methods depend on carrier and fab configurations; microenvironment pods, vacuum chambers, and cleanroom automated material handling systems (AMHS) are distinct stages.
- 01CarrierWafer Enters Processing Equipment
Wafer carriers provide a controlled microenvironment; actual lot sizes and carrier configurations are governed by line operations.
- 02ProcessingExecuting Recipes Across Process Steps
Deposition, photolithography, and etch operations progressively form semiconductor devices and multilayer interconnects.
- 03InspectionObserving and Measuring at Critical Step Milestones
Defect inspection detects excursions; metrology verifies critical dimensions, film thicknesses, and alignment overlays.
- 04TestingWafer Sort Before Dicing and Packaging
Wafer probe testing evaluates circuit functionality and electrical parameters; subsequent packaging and final test determine final device yield.
Tools and Chambers Represent Two Distinct Physical Layers
A tool is the equipment unit; a chamber is the enclosed reactor where processing occurs. Many vacuum deposition and etch tools use cluster architectures: equipment front-end modules (EFEM), load locks, vacuum transfer robots, and process chambers work in coordination. Lithography scanners, chemical mechanical planarization (CMP) polishers, and inspection tools exhibit distinct mechanical architectures.
Chambers of the identical model may have distinct maintenance cycles, consumable lifetimes, and process signatures. Comparative investigations can drill down to chamber level, but engineers must first confirm reliable per-wafer chamber logging.
Routes Specify Planned Steps; History Records What Actually Happened
A Route is the planned manufacturing path; a Recipe defines the parameters and steps for a tool operation; actual history records when a wafer passed through each piece of equipment. Together, they help identify the interval in which an image anomaly may have appeared.
A complete manufacturing route consists of numerous repetitive processing and inspection steps. Not every step captures full-wafer high-resolution images, and not all tool sensors preserve raw waveforms. Data availability must be confirmed case by case.
Repeated Combinations of Core Process Operations
| Operation | Intuitive Role |
|---|---|
| Deposition and Growth | Adds conductive, insulating, or semiconductor thin films. |
| Coat, Expose, and Develop | Defines geometric pattern windows in photoresist. |
| Etching | Removes unmasked target materials; dry plasma etch and wet chemical etch serve distinct purposes. |
| Doping and Thermal Anneal | Modifies electrical properties through ion implantation, activating dopants and repairing crystal lattices. |
| Clean and Strip | Removes surface residues and chemical contaminants while preventing structural substrate damage. |
| CMP Planarization | Achieves global surface planarity through synergistic chemical and mechanical polishing. |
FEOL forms active transistors, MOL forms local contact plugs, and BEOL constructs multilayer metal interconnects. These fabrication stages differ from backend packaging terms, and metal layer counts vary significantly across device architectures.
Wafer Images Are Only One Component of Quality Metrology
Inspection finds anomaly locations; metrology measures dimensions and material properties; WAT/PCM observes electrical process-monitor structures; wafer probe checks chip functionality. Suspect defects do not necessarily cause chip failure, and electrical failures may not be visible in the saved images.
Transforming Manufacturing Routes into Inspectable Context
For example: an anomalous pattern on wafer edges after etch requires verifying whether pre- and post-inspection baselines are comparable, followed by inspecting the etch, photoresist strip, and wet clean histories. Engineers cannot convict a chamber edge focus ring based solely on visual edge rings.
WAFERPILOT / APPLICATION TO THIS TOPIC
Grounding Visual Observations in Physical Manufacturing History
Inputs are wafer images, existing analyses, and available history. WaferPilot organizes image inspection and evidence references to help engineers identify anomaly locations, possible occurrence intervals, and the next check. Deeper cross-step localization depends on data access and method validation.
Deliverables for Engineers:An investigation summary highlighting anomalous wafers, inspection stages, candidate process windows, and prioritized next verification checks.
View the Current Demo and Capability Scope →Related Reading & References
Below are verifiable industry references; specific processes, permissions, and acceptance criteria are governed by fab site specifications.